Present technologies feature metal interconnects with widths as small as 22 nm (e.g., copper interconnects). Future technologies may scale the size of metal interconnects even further. As devices within integrated circuits (ICs) continue to scale, electromigration (EM), stress migration (SM), and line resistance degradation must be reduced.
Small grain sizes within interconnect materials and the prevalent use of high resistivity barriers materials (e.g., TaN/Ta) in conventional semiconductor devices pose challenges to reduce these effects. Additionally, surface scattering and line to line coupling capacitances within metal interconnects should also be addressed to lower line resistance.
Therefore, what is needed is a method to reduce line resistance, EM and SM and optimize the required resistive-capacitance (RC) delay targets in metal interconnects. The present disclosure addresses such a need.